Relıabılıty and Energy Optımızatıon in Hıgh Level Synthesıs of Integrated Cırcuıts

Abstract

Ever-increasing performance demand for the computer applications has resulted in shrinking the technology sizes of the CMOS circuits over the past 50 years, which made it possible to increase the number of transistors on a single chip. On the other hand, the increase in circuit densities makes the design process more challenging. For example, circuits become more vulnerable to radiation effects due to lower supply and threshold voltage levels; thus, the

number of transient faults in circuits increases. While a reduced technology size makes cir- cuits more susceptible to transient faults, some energy reduction techniques also negatively

affect their reliability. Traditional high level synthesis (HLS) methods usually consider only area and latency along with either energy or reliability. To the best of our knowledge, there

is no prior work that takes area and latency as constraints and energy and reliability as op- timization parameters. Especially, the effect of DVS on reliability is completely ignored by

the previous studies. In this work, we aim to develop new HLS methods for application spe- cific integrated circuit (ASIC) design under area and timing constraints with the objectives of

low energy consumption and high reliability. For the mapping and scheduling steps of HLS,

we propose genetic algorithm (GA)-based optimization method, and also use a selective du- plication method. And for comparison purposes we introduced integer linear programming

i

(ILP) method. While the ILP-based method determines the optimum results, the CPU time exponentially increases with the number of the application nodes. Therefore, we propose a GA-based metaheuristic that is faster and determines optimum or near-optimum results in shorter times than ILP. In addition, we characterize a resource library consisting of three adders and two multipliers with varying area, delay, energy, and reliability parameters under two voltage levels.