ENERJİ VERİMLİ KULLANIMA ÖZEL 3D YONGA ÜSTÜ AĞ TASARIMI
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Date
2017-06-14Author
Barzinmehr, Arash
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Network-on-Chip (NoC) is a promising approach for supporting a heavy communication
demand between all parts of high-performance modern nanoscale System-on-Chips (SoCs).
Three-dimensional (3D) IC integration has become popular by reducing latency and energy
consumption due to replacing long global interconnects with short vertical through silicon
via (TSV) interconnects between different dies. Combining NoCs with 3D technology seems
a good choice for achieving better performances than 2D. Although there exist good
synthesis methods for designing energy- and communication-aware 2D-NoCs, there is still
needs for 3D alternative. In this paper an energy-aware application-specific topology
generation method for 3D-NoCs is proposed. This method is based on a heuristic
optimization algorithm that partitions the application nodes among layers of the NoC
architecture for an attempt to minimize the dynamic energy consumption. Proposed 3D
method tested against a 2D alternative through several NoC benchmarks. Simulation results
show that our approach outperforms its 2D counterpart in terms of energy and area.