Investigation of Irregular Network-on-Chip Topologies for Deep Neural Network Accelerators

Abstract

Network-on-Chip (NoC) architectures are essential for enabling efficient and scalable communication in System-on-Chip (SoC) designs, offering flexibility and adaptability for diverse applications. This versatility enables application-specific optimizations, particularly to reduce energy consumption, a critical factor in performance-intensive tasks. Neural Networks (NNs) are one such application that benefits significantly from SoC designs. This study introduces a methodology for generating an optimized irregular NoC topology specifically designed for NN accelerators. We employ a meta-heuristic combinatorial optimization approach based on Simulated Annealing (SA) algorithm. We start with a 2D regular mesh topology, which is randomly disrupted to form an initial irregular configuration. The SA algorithm then explores a wide range of configurations, progressively converging on an energy-efficient irregular NoC topology design. As a result, we observed very promising communication cost improvements ranging from 44% to 89% while generating a topology much more performant when compared to existing methods.