Effıcıent Implementatıon Of Sımplıfıed Aes And Its Sıde-Channel Analysıs

Abstract

Lightweight cryptography is gaining momentum as the number of connected Internet of Things (IoT) devices in the world is expected to reach beyond 50 billion by 2030. With all that massive amount of connectivity, the demand for communication security will be higher as well as the edge processing speed. In this thesis, the Simplified AES (S-AES) algorithm, a popular, fast and feasible solution for the security of embedded devices concerning other ultra-lightweight block ciphers is studied. S-AES has been considered as one of the better options in terms of memory usage in microcontrollers, where memory is already in high demand. In this thesis, the S-AES encryption performance was improved by simple, yet efficient techniques applied on the MixColumns layer. STM32F4-DISCOVERY board having an ARM Cortex-M4 embedded processor is used to demonstrate these techniques while relatively comparing them concerning each other to show the performance improvements. Additionally, Altera Cyclone-IV and Xilinx BASYS-3 FPGA demo boards are used to demonstrate the high performance and low-area implementation of this algorithm compared to other lightweight block ciphers. Side-channel security of the implementation techniques was analyzed on STM32F4-DISCOVERY board to prove the implementation is still secure even though the performance is improved. As a conclusion, the embedded software and hardware implementations of S-AES showed that this encryption algorithm can be used in performance-critical areas such as Internet of Things (IoT).