Implementation of a Neural Network Application Using Accelerator on Risc-V Architecture in Fpga

Abstract

Nowadays, smart devices and Internet of Things (IoT) devices have become an indispensable part of our lives. Especially, IoT devices have taken an important place in every part of our lives with the changing life conditions and the development of technology. While it is estimated that there are approximately 800 million IoT devices and 8 billion other electronic devices in the world in 2010 [1]. This number is around 16 billion for IoT devices and around 10 billion for other devices in 2022[1]. With this increase, the number of IoT devices re predicted to overrun 30 billion in 2030 [2]. On the other hand, due to the Covid-19 pandemic in 2020 a production crisis occurs in the chip industry. Chip prices have increased of Intel, Advanced Micro Devices, Inc. (AMD) and Advanced RISC Machine Inc. (ARM) chips, which are currently being sold at high prices compared to 2019, have increased even more [3]. In this context, work on the RISC-V architecture, which is intended to be developed as a competitor to Intel, AMD and ARM architectures, has accelerated. With the increase in studies on RISC-V, the RISCV-V architecture is seen as a competitor to the ARM architecture [4]. In this thesis, the Instruction Set Architecture (ISA) called RISC-V, which was developed as open source, was examined. For the RISC-V architecture to compete with current architectures, it has been thought that it should be able to run complex operations with similar performance to its competitors. In addition, a neural network application was developed using RISC-V architecture and it was discussed that RISC-V architecture could be a good alternative in terms of performance for neural network and image processing applications. For this reason, the performance and operability of the system has been compared to other processor architectures by trying different RISC-V cores and processors running on simulation environment. In the last part of this study, a neural network supported object recognition based image processing application is developed and has been tested on the Xilinx Zynq UltraScale+ MPSoC ZCU102 development board by using the RISC-V architecture as a hardware accelerator driver. In this structure, peripheral units in Xilinx Zynq architecture were used and a new accelerator method was proposed using RISC-V architecture. The performance results with other known neural network supported object recognition-based image processing algorithms are examined. As a conclusion, within the scope of this thesis, the RISC-V architecture is shown to be capable of executing neural network applications, image processing applications and providing usability in performance critical IoT devices.