On-Line Application Of Shem By Particle Swarm Optimization To Grid-Connected, Three-Phase, Two-Level Vscs With Variable Dc Link Voltage
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Date
2018Author
Guvengir, Umut
Cadirci, Isik
Ermis, Muammer
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This paper is devoted to an otablen-line application of the selective harmonic elimination method (SHEM) to three-phase, two-level, grid-connected voltage source converters (VSCs) by particle swarm optimization (PSO). In such systems, active power can be controlled by the phase shift angle, and reactive power by the modulation index, against variations in the direct current (DC) link voltage. Some selected, low-odd-order harmonic components in the line-to-neutral output voltage waveforms are eliminated by calculating the SHEM angle set continuously through the developed PSO algorithm on field-programmable gate array (FPGA)-based computing hardware as the modulation index is varied. The use of powerful computing hardware permits the elimination of all harmonics up to 50th. The cost function of the developed PSO algorithm is formulated by using an optimum number of particles to obtain a global optimum solution with a small fitness value in each half-cycle of the grid voltage and then updating the SHEM angle set at the beginning of the next full-cycle. Since the convergence of the solution to a global minimum point depends upon the use of correct initial values especially for a large number of SHEM angles, a generalized initialization procedure is also described in the paper. Theoretical results are verified initially using hardware co-simulation. They are also tested using a small scale photovoltaic (PV) supply prototype developed specifically for this purpose. It is demonstrated that the 5th, 7th, 11th, 13th, 17th, and 19th sidekick harmonics are eliminated by on-line calculation of seven SHEM angles through the developed PSO algorithm on a moderately powerful XEM6010-LX150, USB-2.0-integrated FPGA module. All control and protection actions and the calculation of SHEM angles are achieved by a single FPGA chip and its peripherals within the FPGA board.