Yonga-Üstü-Ağlar için Uygulamaya Özgü Yeniden Yapılandırılabilir Topoloji Tasarımı

Abstract

The rapid reduction in integrated circuit dimensions makes it possible to place more components on a single chip in each generation. While the increase in components requires a better communication mechanism than traditional wiring-based communication methods, new design algorithms are needed to tolerate increasing permanent failures due to shrinking technology dimensions. To solve the problem, the network-on-chip (NoC) paradigm was developed to keep pace with the communication demands on these very large systems. When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance.

Within the scope of the thesis, firstly we provide a fault-tolerant topology generation method that can tolerate single permanent link failure on a NoC architecture that is designed for a particular application. The generated topologies provide fault-tolerance by providing at least two alternative paths between the application's communicating nodes. The method is a genetic algorithm based method, which generates an initial population based on ring topology and produces better irregular topologies in terms of energy consumption through genetic operators. The objective function of the proposed method is to minimize the energy consumption resulting from network communication.

There are at least two paths between system components in an application-specific fault tolerant topologies. However, if a fault occurs on the links during the chip's running time, the data cannot be correctly transmitted to the destination router. Therefore, we propose a mechanism that detects errors dynamically during the runtime and transmits packets to the destination routers by alternative paths according to the fault condition.

Although mesh topology is most commonly used topology for NoC design, it has several problems such as network congestion and energy consumption. Reconfigurable mesh topology is a good alternative to traditional mesh since it gives more mapping and routing options for reducing network congestion. However, design automation tools still lack efficient mapping and routing algorithms for reconfigurable meshes. In this study, we propose a genetic algorithm (GA) based method that simultaneously maps the application nodes on 2D reconfigurable mesh structure and determines the routing paths between communicating pairs with the objective of energy minimization.

Finally, we present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, it maps the irregular topology, which uses the least amount of routers and links to minimize the area and energy and offers only one routing path between communicating nodes, to the reconfigurable network topology. In the second step, the method decides the paths between the placed nodes.